Research output per year
Research output per year
Personal profile
Research interests
MEMS Fabrication, VLSI design, Thin film gas sensors, Fuel cells, Cantilever based energy harvesters and vibration sensors
Experience
8 years teaching and research experience
Awards and recognition (Provided by external agencies)
6 patents (4 granted, 2 published)
Fingerprint
Dive into the research topics where Arjun Sunil Rao is active. These topic labels come from the works of this person. Together they form a unique fingerprint.
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Collaborations and top research areas from the last five years
Recent external collaboration on country/territory level. Dive into details by clicking on the dots or
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Impact of Forward Body Biasing on Threshold Voltage and Transconductance in n-Channel MOSFETs for Sustainable Electronics
Nagendran, S., Naveen, J., Taran, P. A., Rao, A. S. & Sannakashappanavar, B. S., 2027, Intelligent Systems and Sustainable Computing - Advancements in Computational Intelligence: Proceedings of ICISSC 2024. Latha, Y. M., Reddy, V. S., Reddy, K. T. V. & Wang, J. (eds.). Springer Science and Business Media Deutschland GmbH, p. 459-471 13 p. (Smart Innovation, Systems and Technologies; vol. 486 SIST).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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A study of methanol dilution and substrate temperature on phase transition dynamics and functional properties of V2O5 thin films for sustainable technologies
Bhagyashree, K., Aswathi, T., Rao, A. S., Sannakashappanavar, B. S., De, S., Jayarama, A., Pinto, R. & Mahendra, H. N., 12-2026, In: Discover Materials. 6, 1, 256.Research output: Contribution to journal › Article › peer-review
Open Access -
COATI: a chaotic optimization framework for joint eMBB-URLLC scheduling in 5G/6G NR networks
Maninarayana, N., Satapathi, G. S., Karthik, K. S. & Rao, A. S., 09-2026, In: Telecommunication Systems. 89, 3, 107.Research output: Contribution to journal › Article › peer-review
Open Access -
DDX-JK: a data-driven and explainable machine learning framework for reducing circuit simulation overhead in CMOS JK flip-flop designs
Rao, A. S., Roopalakshmi, R., Sharma, S., Nagendran, S., Singal, P., Javeri, A., Kamath, N. & Sriraman, A., 07-2026, In: Discover Applied Sciences. 8, 7, 778.Research output: Contribution to journal › Article › peer-review
Open Access -
High-Speed Adder Design: Propagation Delay Comparison of CMOS RCA and CLA
Disha, M., Preethika, K., Yadav, P. A. T., Naveen, J., Rao, A. S. & Saldanha, J. C., 2026, Proceedings of the 4th IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation, IATMSI 2026. Institute of Electrical and Electronics Engineers Inc., (Proceedings of the 4th IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation, IATMSI 2026).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution