Research output per year
Research output per year
B.E.(ECE),M.E.(DE), Ph.D.(Analog VLSI Signal Processing)
Research activity per year
+30 years
Analog VLSI Signal Processing; CMOS Mixed Signal Design;
Digital and Analog VLSI Deign;
Fractional-order Analog Signal Processing;
Fractional-order Analog Circuits; Bio-medical Signal Processing
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
Research output: Contribution to journal › Article › peer-review
Research output: Contribution to journal › Article › peer-review
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Research output: Contribution to journal › Article › peer-review
Research output: Contribution to journal › Article › peer-review