A Comparitive Study of Propogation Delay and Noise Margin for Various inverter Configurations Using EDA Tools

This research focuses on the study of propagation delay and noise margin for various inverter circuits. The inverter circuits used in this research are CMOS inverter circuit, tristate inverter circuit, pseudo-nMOS inverter circuit and domino inverter circuit. Cadence Virtuoso simulation tool is used to design the schematic and symbol of above-mentioned circuits. gpdk90 is the technology file that is used in this research. Our results shows that the propagation delay followed the trend as follows: CMOS inverter, pseudo-nMOS inverter, domino CMOS inverter and tristate inverter. CMOS inverter circuit produced a least propagation delay of 0.7212 ns followed by pseudo-nMOS inverter circuit with propagation delay of 0.7514 ns followed by domino CMOS inverter circuit with propagation delay of 20.11 ns. Tristate inverter circuit produced the highest propagation delay of 45.73 ns. In addition, all four circuits were studied for their noise margins. It is observed that CMOS inverter and tristate inverter circuit when enabled produced the highest noise margin with NMh=1.53 V and NML =0.386 V. This trend is followed by domino CMOS inverter with NMH=1.127 V and NML=0 114 V. Pseudo-nMOS inverter circuit produced least noise margin of NMH=0.931 V and NML =0.112 V. Our findings show that the pseudo-nMOS inverter circuit is not efficient in handling noise, and it is prone to distortion of signals due to low noise margin.