A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length

Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate lengths. This paper analyses an optimized 5 nm gate length (L_G) n-channel TG Junctionless SOI FinFET by different spacer engineering techniques with hafnium based (Hf_xTi_1-xO₂) high-k dielectric in the gate stack. The device process parameters like dielectric spacer impact, nano-fin geometry variation, and power analysis along with DC, Analog/RF, and linearity metrics at the nanoscale are investigated. To increase the accuracy of results at lower gate lengths, quantum models are involved by using TCAD simulator. The proposed device shows excellent electrical characteristics with DIBL = 10.6 mV/V, SS = 63.6 mV/dec, switching ratio (I_ON/I_OFF) = ~10⁷ and good ON-OFF performance metric Q = g_m/SS = 2.06 × 10⁻⁵ S-dec/μm-mV even at 5 nm L_G. The performance impact of outer low-k spacer dielectric variation in dual-k spacer reveals that performance enhancement of ~77% in terms of switching ratio, reduction of leakage current by ~73%, and improvement of g_m by ~10% have been noticed from SiO₂ + HfO₂ to Si₃N₄ + HfO₂. However, due to high-k dielectric in dual-k spacer gate capacitances increases, which leads to deterioration of RF parameters like f_t, τ, and GBW. The Air single-k spacer shows good performance for RF applications with f_t = 600 GHz, τ = 1 ps, GBW = 1.23 THz and dynamic power = 0.095 fJ/μm at L_G = 5 nm. However, the linearity characteristics deteriorates for dual-k spacers and higher dielectric single-k spacers (SiO₂, Si₃N₄) has been noticed. This investigation reveals that at nanoscale Air spacer outperforms all other spacer combinations for low power applications and better linearity (low distortion), and assures further scaling for RF applications.