A Grid-Tied Voltage Boosting Multilevel Inverter With Reduced Voltage Stress and Part Count

This paper presents a single-phase switched-capacitor (SC)-based boost inverter topology capable of synthesizing a seven-level (7L) output using only nine power switches, two capacitors, and a single DC input source. The proposed topology (PT) achieves a voltage gain of 1.5 while ensuring inherent capacitor voltage self-balancing without the need for complex auxiliary control circuits. A comprehensive analysis of the topology is provided, covering its structural configuration, operational principles, and the embedded self-balancing mechanism. Furthermore, a comparative evaluation with existing topologies is conducted in terms of voltage stress, component count, and cost function to highlight the advantages and limitations of the PT. The theoretical analysis is validated through simulation using a pulse width modulation (PWM) control scheme. Additionally, power loss calculations and the integration of the proposed inverter into a grid-connected photovoltaic (PV) system are explored. The feasibility and performance of the proposed 7L design are further confirmed through both static and dynamic experimental testing.