TY - GEN
T1 - A Hybrid Design for Low-Power Fault Tolerant One-Bit Full Adder for Neural Network Applications
AU - Raji, C.
AU - Prasad, S. N.
N1 - Publisher Copyright:
© 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
PY - 2022
Y1 - 2022
N2 - Artificial neural networks (ANNs) are, nowadays, used for implementing critical applications. However, ANN is not inherently fault tolerant. In the hardware implementation of constituent neuron comprising of adder and multiplier should be made fault tolerant, for the system to perform faultless. The building unit of a neuron or any arithmetic processing unit comprises of adders and by reduction in size of these devices, they are prone to transient errors. The power and area overhead in these implementations along with reliability have to be addressed. Here, a hybrid one-bit adder design is presented which resulted in reduction of 20% in number of transistors used and maintained the outputs at full swing thereby retaining the fidelity of the outputs. Power dissipated by the circuit is optimized to the extent which may be acceptable in any of the applications such as automotive, chip design, multimedia applications, and many more.
AB - Artificial neural networks (ANNs) are, nowadays, used for implementing critical applications. However, ANN is not inherently fault tolerant. In the hardware implementation of constituent neuron comprising of adder and multiplier should be made fault tolerant, for the system to perform faultless. The building unit of a neuron or any arithmetic processing unit comprises of adders and by reduction in size of these devices, they are prone to transient errors. The power and area overhead in these implementations along with reliability have to be addressed. Here, a hybrid one-bit adder design is presented which resulted in reduction of 20% in number of transistors used and maintained the outputs at full swing thereby retaining the fidelity of the outputs. Power dissipated by the circuit is optimized to the extent which may be acceptable in any of the applications such as automotive, chip design, multimedia applications, and many more.
UR - https://www.scopus.com/pages/publications/85130271325
UR - https://www.scopus.com/inward/citedby.url?scp=85130271325&partnerID=8YFLogxK
U2 - 10.1007/978-981-16-8542-2_22
DO - 10.1007/978-981-16-8542-2_22
M3 - Conference contribution
AN - SCOPUS:85130271325
SN - 9789811685415
T3 - Lecture Notes in Electrical Engineering
SP - 277
EP - 293
BT - International Conference on Artificial Intelligence and Sustainable Engineering - Select Proceedings of AISE 2020
A2 - Sanyal, Goutam
A2 - Travieso-González, Carlos M.
A2 - Awasthi, Shashank
A2 - Pinto, Carla M.
A2 - Purushothama, B. R.
PB - Springer Science and Business Media Deutschland GmbH
T2 - International Conference on Artificial Intelligence and Sustainable Engineering, AISE 2020
Y2 - 27 November 2020 through 29 November 2020
ER -