TY - GEN
T1 - A Level-Increment Circuit for Multilevel Inverter Based on Cross-Connected Sources
AU - Dewangan, Niraj Kumar
AU - Gupta, Krishna Kumar
AU - Singh, Mandeep
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Multilevel inverters (MLIs) are growing as a potential solution for DC to AC power conversion. This work describes the design and implementation of a single-phase newly developed multilevel inverter configuration that combines a cross connected sources (CCS) based MLI and a half-bridge inverter with considerable decrease in component count for a large number of output voltage levels. The level-increment circuit (LIC) is a type of half-bridge inverter that boosts the output voltage levels in the CCS-MLI topology by nearly twice. The aforesaid approach minimises the amount of power switching devices utilised compared to conventional topologies, resulting in higher output voltage levels by minimising the THD and dv/dt stress on the load. The proposed configuration can be designed to operate in both symmetrical and asymmetrical source patterns. Symmetrical arrangement allows for the formation of four more levels in each sequence with addition of each pair of switches to the basic module. The concept has been studied using MATLAB/Simulink and a laboratory prototype.
AB - Multilevel inverters (MLIs) are growing as a potential solution for DC to AC power conversion. This work describes the design and implementation of a single-phase newly developed multilevel inverter configuration that combines a cross connected sources (CCS) based MLI and a half-bridge inverter with considerable decrease in component count for a large number of output voltage levels. The level-increment circuit (LIC) is a type of half-bridge inverter that boosts the output voltage levels in the CCS-MLI topology by nearly twice. The aforesaid approach minimises the amount of power switching devices utilised compared to conventional topologies, resulting in higher output voltage levels by minimising the THD and dv/dt stress on the load. The proposed configuration can be designed to operate in both symmetrical and asymmetrical source patterns. Symmetrical arrangement allows for the formation of four more levels in each sequence with addition of each pair of switches to the basic module. The concept has been studied using MATLAB/Simulink and a laboratory prototype.
UR - https://www.scopus.com/pages/publications/85189756601
UR - https://www.scopus.com/pages/publications/85189756601#tab=citedBy
U2 - 10.1109/IFEEC58486.2023.10458583
DO - 10.1109/IFEEC58486.2023.10458583
M3 - Conference contribution
AN - SCOPUS:85189756601
T3 - 2023 International Future Energy Electronics Conference, IFEEC 2023
SP - 404
EP - 409
BT - 2023 International Future Energy Electronics Conference, IFEEC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Future Energy Electronics Conference, IFEEC 2023
Y2 - 20 November 2023 through 23 November 2023
ER -