TY - JOUR
T1 - A Novel Approach to Develop Low Power MACs for 2D Image Filtering
AU - Samanth, Rashmi
AU - Kedlaya K, Vishnumurthy
AU - Nayak, Subramanya G.
N1 - Publisher Copyright:
© 2013 IEEE.
Copyright:
Copyright 2021 Elsevier B.V., All rights reserved.
PY - 2021
Y1 - 2021
N2 - In emerging technologies, a vital role is played by ASIC designs in processor operations. There is a necessity to develop such a processor composed of low power blocks. This paper discusses the design exploration of the fixed-point multiply-accumulate unit to achieve high-speed and low power consumption. A 2D image convolution process is developed by stacking and combining several MAC blocks. The developed MAC comprises a sequential multiplier, controller, and optimized adder units. The entering image pixels and kernel pixels are checked for similarity and accordingly isolated by the controller unit, thereby saving power by eliminating the redundant multiplications. A novel idea of reducing the additions in image filtering operations is incorporated in the design. The performance of the proposed MAC showed a 28% power reduction compared to the conventional approaches.
AB - In emerging technologies, a vital role is played by ASIC designs in processor operations. There is a necessity to develop such a processor composed of low power blocks. This paper discusses the design exploration of the fixed-point multiply-accumulate unit to achieve high-speed and low power consumption. A 2D image convolution process is developed by stacking and combining several MAC blocks. The developed MAC comprises a sequential multiplier, controller, and optimized adder units. The entering image pixels and kernel pixels are checked for similarity and accordingly isolated by the controller unit, thereby saving power by eliminating the redundant multiplications. A novel idea of reducing the additions in image filtering operations is incorporated in the design. The performance of the proposed MAC showed a 28% power reduction compared to the conventional approaches.
UR - http://www.scopus.com/inward/record.url?scp=85100837118&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85100837118&partnerID=8YFLogxK
U2 - 10.1109/ACCESS.2021.3058736
DO - 10.1109/ACCESS.2021.3058736
M3 - Article
AN - SCOPUS:85100837118
SN - 2169-3536
VL - 9
SP - 28421
EP - 28428
JO - IEEE Access
JF - IEEE Access
M1 - 9352751
ER -