A Novel De-Mirroring-based Analytical Model for Capacitance Extraction of Nanosheet FET using Dielectric Permittivity Suppression

Unlike planar MOSFETs, the Nanosheet FET poses a complex capacitor network that captures the sheet geometry, number of sheets, source-gate-drain contacts, intersheet coupling, etc. To date, the existing compact models predominantly rely on the Cold-FET approach (referred to here as ’mirroring’), in which both gate-to-source (V_GS) and drain-to-source (V_DS) voltages are set to zero. However, the mirroring assumption breaks down during the saturation regime of operation, necessitating the V_DS-dependent capacitance model. Thus, this paper proposes a novel de-mirroring approach for capacitance extraction in Nanosheet FET (NSFET). The device is conceptually cleaved at the center of the channel, allowing separate evaluation of V_GS and V_DS-dependent capacitances using a conformal mapping technique. The permittivity suppression method is employed to compute the individual capacitance component. The proposed model shows good agreement with simulation data, which has been calibrated against the experimental data. The results demonstrate that the traditional mirroring approach overestimates the overall gate capacitance (C_gg) by ~15%, whereas the proposed de-mirroring approach provides a significantly more accurate prediction.