A Novel Multiply-Accumulator Unit Bus Encoding Architecture for Image Processing Applications

R. Samanth, S. G. Nayak, P. B. Nempu

Research output: Contribution to journalArticlepeer-review


In the CMOS circuit power dissipation is a major concern for VLSI functional units. With shrinking feature size, increased frequency and power dissipation on the data bus have become the most important factor compared to other parts of the functional units. One of the most important functional units in any processor is the Multiply-Accumulator unit (MAC). The current work focuses on the development of MAC unit bus encoders as well as the identification of an improved architecture for image processing applications. To reduce the power consumption in these functional units, two bus encoding architectures were developed by encoding data before it was sent on the data buses. One is MSB reference encoding, and another is Fourth and Fifth bit ANDing (FFA) without the need for an extra bus line with fewer transitions by using gray codes. The comparison of the proposed encoding architectures with the existing encoding architectures from the literature revealed an 8% to 36% significant improvement in power dissipation. The simulation was done with Xilinx ISE, and the Cadence RTL Compiler tool was utilized for the synthesis, which was done with the 180nm technology library. And also, the image filtering is analyzed using MATLAB.

Original languageEnglish
Article number2391
JournalIranian Journal of Electrical and Electronic Engineering
Issue number1
Publication statusPublished - 03-2023

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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