A novel time-domain in-memory computing unit using STT-MRAM

Advancements in technologies like Big Data, IoT, and AI have revealed a bottleneck in traditional von-Neumann architecture, resulting in high energy consumption and limited memory bandwidth. In-memory computing (IMC) presents a promising solution by enabling computations directly within the memory, enhancing energy-efficient computing. The existing time-domain (TD)-based IMC computations either require multiple cycles for computation through a successive read/write approach or contribute to the complexity of the peripheral circuit by adopting a cumulative delay approach. In this paper, we present a novel array architecture that utilizes spin transfer torque magnetic random access memory (STT-MRAM) bit-cells, mitigating source degeneration issue. By leveraging this advanced technology and employing a TD computing scheme, we have successfully implemented various arithmetic operations, alongside a comprehensive set of Boolean logic operations. Our design demonstrates improved area and energy efficiency compared to other existing TD computing schemes. Furthermore, despite the higher delay, our parameter-driven optimization approach efficiently minimizes it. To validate our proposal, we performed simulations using the 45 nm CMOS process and the Verilog-A based magnetic tunnel junction (MTJ) compact model. Through meticulous Monte-Carlo simulations, considering CMOS variations, the results demonstrate enhanced computational accuracy with increasing Tunnel Magnetoresistance (TMR) ratio, showcasing the potential of our architecture in advancing the field of computing.