A Power-Efficient High-Speed D-Latch Architecture for Enhanced PDP Performance

This paper presents a compact, energy-efficient D-latch architecture that employs a rail-to-rail signal path and balanced complementary nodes to achieve low Power Delay Product (PDP) while maintaining robust timing behavior. The proposed D-latch is implemented in 180 nm CMOS at V_DD = 1.8 V with a 50 fF load and compared against representative D-latch architectures. Simulation results show that the proposed design achieves the lowest PDP of 10.4 fJ, offering an optimal trade-off between delay and power consumption. Post-layout implementation occupies an area of 13.94 μm × 10.26 μm, and extracted simulations confirm correct functionality with a modest D to Q delay increase from 250 ps (pre-layout) to 274.6 ps due to parasitic effects. Scalability is validated through pre-layout simulations in 45 nm CMOS, operated at a supply voltage of 1.8 V, where the proposed latch achieves a D to Q delay of 110 ps, an average power consumption of 33.8 μW, and a power–delay product of 3.70 fJ. These results demonstrate the suitability of the proposed latch for high-speed, energy-efficient digital systems and for low-power design techniques such as clock gating and power gating.