A Reconfigurable IEEE-754 FP32 Fused Multiply Accumulate Architecture with Hybrid Multiplier and Prefix Adder Optimization

The proposed work presents the design, verification, and full RTL-to-GDSII implementation of a single-precision fused multiply-accumulate (FMA) unit that can be changed or reconfigured and follows the IEEE-754 standard. The unit is defined by y = a × b + c. The design incorporates selectable multiplier and adder architectures, such as Booth + CSA, Array, and Vedic hybrid multipliers with Kogge-Stone and Han-Carlson adders. It also has an optional approximate arithmetic mode to minimize dynamic power. The proposed five-stage pipelined datapath delivers high throughput with a balanced latency profile while keeping IEEE-754 rounding accuracy and special-case handling. Using Cadence tools, we carried out functional and physical verification, which showed that the power and area were being used efficiently. Using Cadence Genus-Innovus flow, the design was tested in a 90 nm CMOS technology node. It worked at a maximum frequency of 175 MHz with positive slack and a total power of 33.55 mW in a layout footprint of 48,197 μm2. A comparative evaluation shows that the reconfigurable architecture has a better balance of performance, power, and flexibility than traditional fixed datapaths. The proposed work addresses Sustainable Developmental Goals 4 and 9.