A Study on Propagation Delay and Dynamic Power Dissipation of Inverter Architectures Using Cadence Gpdk90

This research focuses on the study of propagation delay and dynamic power dissipation for various inverter circuits. The inverter circuits used in this research are static CMOS inverter, clocked CMOS (C2 MOS) inverter circuit, nMOS logic inverter circuit and dynamic CMOS inverter circuit. Cadence Virtuoso simulation tool is used to design the schematic and symbol of above-mentioned circuits. gpdk90 is the technology file that is used in this research. Our results show that the propagation delay followed the trend as follows: nMOS logic inverter, dynamic CMOS inverter, static CMOS inverter and C2 MOS inverter, nMOS logic inverter circuit produced a least propagation delay of 0.0475 ns followed by dynamic CMOS inverter circuit with propagation delay of 0.575 ns followed by static CMOS inverter circuit with propagation delay of 0.7212 ns. C2MOS inverter circuit produced the highest propagation delay of 10.256 ns, thereby indicating nMOS logic inverter is faster in processing the signal as compared to the other types. The dynamic power dissipation of dynamic CMOS inverter, C2 MOS inverter circuit, nMOS logic inverter and static CMOS inverter circuits are found to be 1.021 mW, 0.6686 mW, 0.2201 mW and 0.1849 mW, respectively. This indicates the potential application of these circuits in low power VLSI circuits.