An Efficient High Performance GDI based 4-bit Vedic Multiplier in 32nm Technology

System performance improves with good multiplier performance. In today's digital world, the speed of the multiplier is a crucial factor, but it also has a high power consumption. Power and delay optimisation of multipliers will be pivotal. The choice of adder units in the multiplier also takes into account adders such the Ripple carry adder(RCA), carry look-ahead adder(CLA), and carry skip adder(CSA). This research investigates the differences between several adders implemented in Vedic multiplier using CMOS, transmission gate and GDI based techniques. When attempting to design a Vedic multiplier with CMOS transistors and Transmission gates, the circuit will experience problems such as delay, power and area metrics. These problems can be addressed by employing the Gate Diffusion Input (GDI) logic. This uses GDI logic to keep delay, power, and the number of transistors as low as feasible. In this research, a GDI-based 4-bit Vedic multiplier was built in 32nm technology and compared to a CMOS and TG-based vedic multiplier design. GDI-based 4-bit Vedic Multiplier systems were faster, used less power, and took up less area than CMOS and TG-based systems. This 4-bit Vedic multiplier design can be used in the Tanner EDA tool with different adders.