TY - GEN
T1 - An efficient way of implementing high speed 4-Bit advanced multipliers in FPGA
AU - Martha, Pramod
AU - Kajal, Nidhi
AU - Kumari, Priya
AU - Rahul, R.
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/9/13
Y1 - 2018/9/13
N2 - ALU in Digital processor is the important block as all the computational operations carried out by this. A multiplier is an electronic circuit used in any computing device for multiplication of two binary numbers. Multiplication of 4-bit numbers is a lengthy procedure if we go the conventional way. In this paper, two 4 bit multipliers purposed namely Unsigned Array Multiplier and Wallace Tree Multiplier. The Wallace tree method is highly pipelined and saves a lot of time. Individual components of both the devices are optimized and have been used to construct the multipliers. The designed circuit is implemented in FPGA (BASYS-3 ARTIX-7). The delay obtained in Wallace multiplier is 6.86ns,49.35% reduction in delay compared to previous literature. Also, the power consumption is also very low(3.81watt) for Wallace tree multiplier.
AB - ALU in Digital processor is the important block as all the computational operations carried out by this. A multiplier is an electronic circuit used in any computing device for multiplication of two binary numbers. Multiplication of 4-bit numbers is a lengthy procedure if we go the conventional way. In this paper, two 4 bit multipliers purposed namely Unsigned Array Multiplier and Wallace Tree Multiplier. The Wallace tree method is highly pipelined and saves a lot of time. Individual components of both the devices are optimized and have been used to construct the multipliers. The designed circuit is implemented in FPGA (BASYS-3 ARTIX-7). The delay obtained in Wallace multiplier is 6.86ns,49.35% reduction in delay compared to previous literature. Also, the power consumption is also very low(3.81watt) for Wallace tree multiplier.
UR - https://www.scopus.com/pages/publications/85054508864
UR - https://www.scopus.com/pages/publications/85054508864#tab=citedBy
U2 - 10.1109/IEMENTECH.2018.8465375
DO - 10.1109/IEMENTECH.2018.8465375
M3 - Conference contribution
AN - SCOPUS:85054508864
SN - 9781538655498
T3 - 2018 2nd International Conference on Electronics, Materials Engineering and Nano-Technology, IEMENTech 2018
BT - 2018 2nd International Conference on Electronics, Materials Engineering and Nano-Technology, IEMENTech 2018
A2 - Sarkar, Mili
A2 - Chakrabarty, Ratna
A2 - Taki, G. S.
A2 - Chakrabarti, Satyajit
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd International Conference on Electronics, Materials Engineering and Nano-Technology, IEMENTech 2018
Y2 - 4 April 2018 through 5 April 2018
ER -