An energy-efficient D-latch architecture with feedforward technique for high-speed applications

This work presents a novel delay-optimized D-latch architecture that enhances speed performance through the introduction of additional parallel discharge paths at the output node. A Path Enable Block (PEB), placed at the output and controlled by both the clock and feedforward data signal (D), selectively activates these discharge paths during critical transitions. The optimal number of parallel paths (N) is determined based on the load capacitance to ensure minimal delay with controlled power overhead. The proposed architecture is first implemented in 180 nm CMOS technology using Cadence Virtuoso at a supply voltage of 1.8 V, achieving a D-to-Q delay of 0.291 ns and a Power Delay Product (PDP) of 17.67 fJ for a 50 fF load with N=6. Furthermore, the proposed latch supports a maximum operating frequency of 1.6 GHz under a 50 fF load, making it well-suited for integration in high-speed, energy-efficient systems such as IoT devices, wearable electronics, and low-power digital processors. To evaluate scalability and energy efficiency in advanced nodes, the same design is implemented in 45 nm technology with a supply voltage of 1.2 V, where the delay is further reduced to 0.221 ns with a significantly lower PDP of 4.08 fJ. Notably, simulations were also performed at a fixed V_DD of 1.8 V across both nodes to isolate the impact of architectural enhancements from supply voltage scaling. Results confirm that the observed improvements stem from the proposed circuit technique itself, independent of V_DD reduction.