An Energy Efficient Multilevel Reconfigurable parallel Cache Architecture for Embedded Multicore Processors

In modern multicore processors, a major portion of the total power consumption is accounted towards the cache memory. Moreover the performance disparity between the processor and memory is becoming a massive disadvantage. When it comes to performance, cache misses have become very costly, needing to access primary memory (DRAM) which can be 150 times slower than the direct access from L1-caches (SRAM). Therefore optimized energy-aware cache design techniques are very essential for today's high-performance processors. As the device area is steadily decreasing; it is highly possible to integrate within the existing embedded multiprocessor architecture, new cache architectures like Location caches, Filter caches and Victim caches for improving the overall performance as well as efficiency. But each of these configurations has their own pros and cons with respect to various applications. Here an attempt is made to modify the existing embedded processor architecture with these added multilevel Cache Architectures in a reconfigurable mode, such that the system can adapt intelligently to the run-time demands successfully. An Intelligent Dynamic controller based on Fuzzy Logic is used to select the exact combination of the above cache layers suited for specific applications, ranging from extremely low power mode, Digital Signal or image processing mode to High performance (Real-time operation) mode. Experiments conducted using CACTI simulator shows better efficiency can be achieved by selecting the appropriate cache layers according to the specific demands of the applications.