Analog/RF and Linearity Performance Assessment of a Negative Capacitance FinFET Using High Threshold Voltage Techniques

The continued exploration of the ferroelectric-based negative capacitance field effect transistor (NCFET) for energy-efficient and higher current drivability merits has called for an investigation of the device compatibility for analog/RF applications. In this article, we assessed the analog/RF and linearity performance of NC-FinFET by employing high threshold voltage (HVT) techniques. Such techniques are essential to suppress the leakage current and improve the performance in scaled devices. Using well-calibrated TCAD models, we present insight into the advent of incorporating three different HVT approaches: 1) increase in the channel doping (Nch′), 2) drain underlap architecture (Ldsu), and 3) increase in the channel length (Lg') to investigate the analog/RF behavior. Further, various linearity figure-of-merits (FoMs) has been examined using gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point. We also varied Nch′, Ldsu, and Lg' to optimize the proposed HVT techniques for optimum performance. Moreover, the Gummel symmetry test, as a linearity measure, has been done for the optimized HVT-NCFinFET to investigate the drain current symmetry. Thus, the obtained results serve as a design guideline for adopting the NC-FinFET pertaining to low-power RF applications.