Analysis of MTJ write circuits and design of hybrid MTJ/CMOS full adder for in-memory computation architecture

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) in-memory computation (IMC) has emerged as a future computing architecture that mitigates the memory wall and energy wastage problems observed in the conventional von-Neuman structure. However, the energy consumption during the MTJ write process is still a concern in present-day ultra-low power applications. Hence, in this work, we have investigated various types of contemporary MTJ write circuits that work on the principle of spin transfer torque (STT), spin-Hall effect assisted STT (SHE+STT), and voltage-gated spin orbit torque (VG+SOT) writing mechanisms. Using Cadence Virtuoso, the performances of all the write circuits are investigated in terms of metrics such as energy consumption, writing delay, energy delay product, and device count to propose the best among them. Subsequently, we developed a non-volatile full adder with the best MTJ writing circuit, which show a significant performance improvement compared to traditional design in terms of metrics such as read/write power, read delay and read/write power delay product. Further, Monte-Carlo simulations were performed to determine the power variation that can occur during the fabrication process.