Analysis of multi-bridge-channel FET for CMOS logic applications

This study analyses the vertically stacked GAA Multi-Bridge-Channel FETs like Nanosheet at the device level for CMOS applications. Studies are carried out to validate the impact of geometric deviations concerning thickness and width of the FET’s performance. The study also investigates the process parameter variation on DC metrics like threshold voltage (V_th), subthreshold swing (SS), ON-time (I_ON), OFF-time (I_OFF), I_ON/I_OFF, and DIBL. The device achieves better performance by optimizing Nanosheet width (N_W) and thickness (N_T) variability which ensures scaling flexibility. The CADENCE tool is used to investigate the device’s performance in terms of circuit applications. Various circuits like CMOS inverter transient response, switching characteristics, voltage transfer characteristics (VTC) and noise margins are evaluated. The CMOS inverter energy delay product (EDP) and power delay product (PDP) are also analyzed. The PDP and EDP increase by 2.51x and 3.06x with rise of N_W. The CMOS inverter noise margins (NMs) are calculated towards digital circuit applications. The proposed Nanosheet FET has good electrostatic integrity due to its GAA structure, thus, it is a strong contender for low-power and high-performance applications for future technological nodes.