TY - GEN
T1 - Analytical Model of Subthreshold Swing for Cryogenic-CMOS Considering Temperature Dependent Slope Factor
AU - Shakir, Mohd
AU - Bagga, N.
AU - Tiwari, Y.
AU - Malvika,
AU - Singh, P.
AU - Rathore, S.
AU - Ranjan, S.
AU - Dasgupta, S.
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - Assessing the subthreshold behavior of the transistor is crucially important at cryogenic temperatures for the realization of quantum-compatible electronics. In the cryogenic regime, traditional thermal models fail to capture anomalies in the subthreshold region, such as band-tail states, incomplete dopant ionization, source-to-drain tunneling (SDT), and interface traps, thereby strongly influencing the subthreshold swing (SS). This work presents a semi-empirical temperature-dependent slope factor (n) model for a 28nm industry-standard bulk MOSFET, capturing the combined effects of thermionic emission, trap-assisted conduction, and SDT. The calibration and validation of the model are performed using the GTS TCAD tool, with a temperature ranging from 298 to 4.2K. Moreover, the SS behavior of the baseline Cryo-CMOS is investigated with various parameters, including channel length, substrate doping, and oxide thickness, which gives a clear insight into the device design guidelines for deep-cryogenic temperatures.
AB - Assessing the subthreshold behavior of the transistor is crucially important at cryogenic temperatures for the realization of quantum-compatible electronics. In the cryogenic regime, traditional thermal models fail to capture anomalies in the subthreshold region, such as band-tail states, incomplete dopant ionization, source-to-drain tunneling (SDT), and interface traps, thereby strongly influencing the subthreshold swing (SS). This work presents a semi-empirical temperature-dependent slope factor (n) model for a 28nm industry-standard bulk MOSFET, capturing the combined effects of thermionic emission, trap-assisted conduction, and SDT. The calibration and validation of the model are performed using the GTS TCAD tool, with a temperature ranging from 298 to 4.2K. Moreover, the SS behavior of the baseline Cryo-CMOS is investigated with various parameters, including channel length, substrate doping, and oxide thickness, which gives a clear insight into the device design guidelines for deep-cryogenic temperatures.
UR - https://www.scopus.com/pages/publications/105040785179
UR - https://www.scopus.com/pages/publications/105040785179#tab=citedBy
U2 - 10.1109/EDTM65772.2026.11497155
DO - 10.1109/EDTM65772.2026.11497155
M3 - Conference contribution
AN - SCOPUS:105040785179
T3 - 10th IEEE Electron Devices Technology and Manufacturing Conference: Emerging Semiconductor Devices and Manufacturing Technologies, EDTM 2026
BT - 10th IEEE Electron Devices Technology and Manufacturing Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 10th IEEE Electron Devices Technology and Manufacturing Conference: Emerging Semiconductor Devices and Manufacturing Technologies, EDTM 2026
Y2 - 1 March 2026 through 4 March 2026
ER -