TY - GEN
T1 - ASIC Design and Implementation of a Power-Delay Product Optimized Arithmetic Operational Unit
AU - Mendez, Tanya
AU - Nayak, Subramanya G.
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - The architectural design of a 16-bit arithmetic operational unit that has an optimized power-delay product is introduced using the technique of iterative carry-save addition and error-tolerant addition. The incorporation of Low-Power Selector Based Error-Tolerant Adders in the design and implementation of the iterative carry-save adder and multiplier enhances the speed and lowers the power consumption. The proposed arithmetic operational unit is modelled using Verilog hardware description language. The ASIC implementation and synthesis is performed using Cadence Genus tool with 45 and 90 nm gpdk standard technology libraries. A considerable reduction was noticed in the power, delay, and PDP of the proposed arithmetic operational unit.
AB - The architectural design of a 16-bit arithmetic operational unit that has an optimized power-delay product is introduced using the technique of iterative carry-save addition and error-tolerant addition. The incorporation of Low-Power Selector Based Error-Tolerant Adders in the design and implementation of the iterative carry-save adder and multiplier enhances the speed and lowers the power consumption. The proposed arithmetic operational unit is modelled using Verilog hardware description language. The ASIC implementation and synthesis is performed using Cadence Genus tool with 45 and 90 nm gpdk standard technology libraries. A considerable reduction was noticed in the power, delay, and PDP of the proposed arithmetic operational unit.
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U2 - 10.1109/MoSICom59118.2023.10458728
DO - 10.1109/MoSICom59118.2023.10458728
M3 - Conference contribution
AN - SCOPUS:85190107502
T3 - Proceedings of IEEE International Conference on Modelling, Simulation and Intelligent Computing, MoSICom 2023
SP - 59
EP - 64
BT - Proceedings of IEEE International Conference on Modelling, Simulation and Intelligent Computing, MoSICom 2023
A2 - Nayak, Jagadish
A2 - Gaidhane, Vilas H
A2 - Goel, Nilesh
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE International Conference on Modelling, Simulation and Intelligent Computing, MoSICom 2023
Y2 - 7 December 2023 through 9 December 2023
ER -