ASIC implementation of DDR SDRAM memory controller

Amit Bakshi; Sudhanshu Shekhar Pandey; Tribikram Pradhan; Ratnadip Dey

doi:10.1109/ICE-CCN.2013.6528467

ASIC implementation of DDR SDRAM memory controller

Amit Bakshi
, Sudhanshu Shekhar Pandey
, Tribikram Pradhan
, Ratnadip Dey

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

A Dedicated Memory Controller is of prime importance in applications that do not contain microprocessors (high-end applications). The Memory Controller provides command signals for memory refresh, read and write operation and initialization of SDRAM. Our work will focus on ASIC Design methodology of Double Data Rate (DDR) SDRAM Controller that is located between the DDR SDRAM and Bus Master. The Controller simplifies the SDRAM command interface to standard system read/write interface and also optimizes the access time of read/write cycle. Double Data Rate (DDR) SDRAM Controller is implemented using Cadence RTL Compiler.

Original language	English
Title of host publication	2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013
Pages	74-78
Number of pages	5
DOIs	https://doi.org/10.1109/ICE-CCN.2013.6528467
Publication status	Published - 2013
Event	2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013 - Tirunelveli, India Duration: 25-03-2013 → 26-03-2013

Publication series

Name	2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013

Conference

Conference	2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013
Country/Territory	India
City	Tirunelveli
Period	25-03-13 → 26-03-13

All Science Journal Classification (ASJC) codes

Computer Networks and Communications

Access to Document

10.1109/ICE-CCN.2013.6528467

Cite this

Bakshi, A., Pandey, S. S., Pradhan, T., & Dey, R. (2013). ASIC implementation of DDR SDRAM memory controller. In 2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013 (pp. 74-78). Article 6528467 (2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013). https://doi.org/10.1109/ICE-CCN.2013.6528467

Bakshi, Amit ; Pandey, Sudhanshu Shekhar ; Pradhan, Tribikram et al. / ASIC implementation of DDR SDRAM memory controller. 2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013. 2013. pp. 74-78 (2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013).

@inproceedings{2517e454d16f4b52b213ccb879df782d,

title = "ASIC implementation of DDR SDRAM memory controller",

abstract = "A Dedicated Memory Controller is of prime importance in applications that do not contain microprocessors (high-end applications). The Memory Controller provides command signals for memory refresh, read and write operation and initialization of SDRAM. Our work will focus on ASIC Design methodology of Double Data Rate (DDR) SDRAM Controller that is located between the DDR SDRAM and Bus Master. The Controller simplifies the SDRAM command interface to standard system read/write interface and also optimizes the access time of read/write cycle. Double Data Rate (DDR) SDRAM Controller is implemented using Cadence RTL Compiler.",

author = "Amit Bakshi and Pandey, \{Sudhanshu Shekhar\} and Tribikram Pradhan and Ratnadip Dey",

year = "2013",

doi = "10.1109/ICE-CCN.2013.6528467",

language = "English",

isbn = "9781467350365",

series = "2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013",

pages = "74--78",

booktitle = "2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013",

note = "2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013 ; Conference date: 25-03-2013 Through 26-03-2013",

}

Bakshi, A, Pandey, SS, Pradhan, T & Dey, R 2013, ASIC implementation of DDR SDRAM memory controller. in 2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013., 6528467, 2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013, pp. 74-78, 2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013, Tirunelveli, India, 25-03-13. https://doi.org/10.1109/ICE-CCN.2013.6528467

ASIC implementation of DDR SDRAM memory controller. / Bakshi, Amit; Pandey, Sudhanshu Shekhar; Pradhan, Tribikram et al.
2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013. 2013. p. 74-78 6528467 (2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - ASIC implementation of DDR SDRAM memory controller

AU - Bakshi, Amit

AU - Pandey, Sudhanshu Shekhar

AU - Pradhan, Tribikram

AU - Dey, Ratnadip

PY - 2013

Y1 - 2013

N2 - A Dedicated Memory Controller is of prime importance in applications that do not contain microprocessors (high-end applications). The Memory Controller provides command signals for memory refresh, read and write operation and initialization of SDRAM. Our work will focus on ASIC Design methodology of Double Data Rate (DDR) SDRAM Controller that is located between the DDR SDRAM and Bus Master. The Controller simplifies the SDRAM command interface to standard system read/write interface and also optimizes the access time of read/write cycle. Double Data Rate (DDR) SDRAM Controller is implemented using Cadence RTL Compiler.

AB - A Dedicated Memory Controller is of prime importance in applications that do not contain microprocessors (high-end applications). The Memory Controller provides command signals for memory refresh, read and write operation and initialization of SDRAM. Our work will focus on ASIC Design methodology of Double Data Rate (DDR) SDRAM Controller that is located between the DDR SDRAM and Bus Master. The Controller simplifies the SDRAM command interface to standard system read/write interface and also optimizes the access time of read/write cycle. Double Data Rate (DDR) SDRAM Controller is implemented using Cadence RTL Compiler.

UR - https://www.scopus.com/pages/publications/84881036409

UR - https://www.scopus.com/pages/publications/84881036409#tab=citedBy

U2 - 10.1109/ICE-CCN.2013.6528467

DO - 10.1109/ICE-CCN.2013.6528467

M3 - Conference contribution

AN - SCOPUS:84881036409

SN - 9781467350365

T3 - 2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013

SP - 74

EP - 78

BT - 2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013

T2 - 2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013

Y2 - 25 March 2013 through 26 March 2013

ER -

Bakshi A, Pandey SS, Pradhan T, Dey R. ASIC implementation of DDR SDRAM memory controller. In 2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013. 2013. p. 74-78. 6528467. (2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013). doi: 10.1109/ICE-CCN.2013.6528467

ASIC implementation of DDR SDRAM memory controller

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