Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

One of the severe issues of the downscaling of semiconductor devices is the threshold voltage reduction which significantly increases the leakage current. Thus, high threshold voltage (HVT) techniques are required to bring down the leakage hike for improved performances. In this paper, for the first time, we investigate the analog/radio frequency (RF) and linearity performances of silicon (Si) FinFET by employing HVT techniques. Using well-calibrated technology computer aided design models, to mitigate the leakage current, we analyzed the following approach to get HVT: (a) increasing channel doping (N ch′); (b) making drain-side underlap (L dsu); (c) increasing gate length (L g′). Two flavors of fin field effect transistors (FinFETs) viz bulk and silicon-on-insulator (SOI) are suitably compared over their baseline counterpart, i.e. without HVTs. A thorough investigation of analog/RF metrics such as transconductance, output resistance, gate capacitance, cut-off frequency, gain-bandwidth, and transconductance-frequency product proves the eminence of bulk-FinFET over its peer SOI-FinFET. In contrast, SOI-FinFET shows merits in intrinsic gain and linearity such as g m2, g m3, VIP2, VIP3, IIP3, IMD3, and 1 dB compression point. Thus, HVT techniques are worth analyzing for a FinFET architecture employed in analog/RF applications.