Basic operation principle of optimized NCFET: Amplification perspective

To keep alive dimensional scaling, the never-ending progress of modern technology has sparked a plethora of exploratory computing and data storage studies. This has resulted in the search for new device structures, physical phenomena, and circuit topologies. Several device architectures such as tunnel FET, phase FET, and hybrid FET are being investigated to enable ultra-low-power circuit operation using sub-60 mV/decade (sub-kT/q) switching. These new exploratory devices have distinct potentials and constraints that must be thoroughly investigated before moving forward with their commercialization. One such device, 'negative capacitance-based FET,' has attained much attention in recent years due to its compatibility with the CMOS process and direct and indirect experimental evidence. The unique property in some ferroelectric/antiferroelectric oxide materials helps in keeping alive the dimensional scaling at lower technology nodes in NCFET. This chapter opens with a discussion of the material viewpoint, including the selection and optimization of an essential geometrical parameter, namely thickness in negative capacitance materials. The basic notions of negative capacitance's physical origin, stability, and history in attaining steep switching benefits in FETs are reviewed. Various modeling approaches, such as the major-minor hysteresis loop, multi-domain switching, and S-curve employing Landau, as well as the Prieasch model of negative capacitance, are explored. The advantages and disadvantages of various device architectures in the creation of NCFETs such as M-F-M-I-S and M-F-I-S for low-power applications are investigated. Finally, key NCFET features, such as DIBL and NDR, are discussed in order to achieve performance gains in low-power steep switching as well as memory applications.