Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire field-effect-transistor (FET) for significantly enhanced performance at sub-5 nm nodes. The symmetric and asymmetric spacer lengths are optimized and compared towards the improvement of subthreshold swing (SS) and switching ([Formula presented]) behavior with various spacer dielectrics. For optimal values of source (L_S) and drain (L_D) spacer lengths, the device [Formula presented] ratio has an improvement of 22.69% and a reduction in I_OFF by 34.13% as compared to other variations. Our study reveals that, in symmetric spacer variations the device exhibits superior performance with L_S=L_D=1.5×L_G. However, compared to symmetric, the asymmetric spacer exhibits higher [Formula presented] and lower SS with L_S=1.5×L_G and L_D=2.5×L_G. Moreover, L_G scaling impact on SS, DIBL, V_th, and I_ON are reported with various spacers. The optimized asymmetric spacer exhibits excellent DC characteristics with SS of 64 mV/dec and [Formula presented] ratio of ∼10⁸ even for 5 nm gate length (L_G) ensures fundamental scaling. At L_G of 10 nm with asymmetric spacer, a cut-off frequency (f_T) = 0.4 THz, gain-bandwidth product (GBW) = 0.08 THz, and intrinsic delay (τ) = 1.3 ps are achieved. Finally, the device exhibits second order harmonic (g_m2) = 0.2 mA/V² and third order harmonic (g_m3) = 1.1 mA/V³ at nano-regime. Thus optimally designed JL nanowire FET ensures potential candidate towards low-power, high frequency, and better linearity for future technology nodes.