TY - GEN
T1 - Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs
AU - Sai Kumar, Aruru
AU - Deekshana, M.
AU - Bharath Sreenivasulu, V.
AU - Prasad Somineni, Rajendra
AU - Kanthi Sudha, D.
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - According to Moore's law, there have been numerous technological advancements that are currently being processed. The controllability of the device has improved significantly since a basic MOSFET with a single control gate was changed to one with many control gates. This study examines the DC metrics of a sub-5 nm node, junctionless gate, and vertically stacked nanowire field effect transistor (FET). In order to improve the factors ION, IOFF, switching ratio (ION/IOFF), DIBL, and Sub threshold Swing, the device is tuned and compared. Here, a variety of dielectric-permitivity (k) values and symmetric and asymmetric spacing are employed with spacers. 3D-VTCAD is the tool used to evaluate these characteristics. Therefore, a JL nanowire FET with the best design guarantees that it can be a candidate for low-power and superior linearity technology nodes in the future.
AB - According to Moore's law, there have been numerous technological advancements that are currently being processed. The controllability of the device has improved significantly since a basic MOSFET with a single control gate was changed to one with many control gates. This study examines the DC metrics of a sub-5 nm node, junctionless gate, and vertically stacked nanowire field effect transistor (FET). In order to improve the factors ION, IOFF, switching ratio (ION/IOFF), DIBL, and Sub threshold Swing, the device is tuned and compared. Here, a variety of dielectric-permitivity (k) values and symmetric and asymmetric spacing are employed with spacers. 3D-VTCAD is the tool used to evaluate these characteristics. Therefore, a JL nanowire FET with the best design guarantees that it can be a candidate for low-power and superior linearity technology nodes in the future.
UR - https://www.scopus.com/pages/publications/85146336868
UR - https://www.scopus.com/pages/publications/85146336868#tab=citedBy
U2 - 10.1109/ICCCNT54827.2022.9984269
DO - 10.1109/ICCCNT54827.2022.9984269
M3 - Conference contribution
AN - SCOPUS:85146336868
T3 - 2022 13th International Conference on Computing Communication and Networking Technologies, ICCCNT 2022
BT - 2022 13th International Conference on Computing Communication and Networking Technologies, ICCCNT 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 13th International Conference on Computing Communication and Networking Technologies, ICCCNT 2022
Y2 - 3 October 2022 through 5 October 2022
ER -