TY - GEN
T1 - Comparative study of 7T, 8T, 9T and 10T SRAM with conventional 6T SRAM cell using 180 nm technology
AU - Joshi, Vinod Kumar
AU - Lobo, Haniel Craig
N1 - Publisher Copyright:
© Springer Science+Business Media Singapore 2016.
PY - 2016
Y1 - 2016
N2 - Data stability and power consumption have been reported two important issues with scaling of CMOS technology. In this paper, we have revisited these issues on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM). The read/write delay and power consumption has been found 0.671/0.267 ns, 1.69 μW for 6T SRAM cell, 0.456/0.752 ns, 1.09 μW for 7T SRAM cell, 0.517/0.392 ns, 1.82 μW for 8T SRAM cell, 0.388/0.181 ns, 1.3 μW for 9T SRAM cell and 0.167/0.242 ns, 2.01 μW for 10T SRAM cell respectively. SNM has been calculated 0.4 V for 6T SRAM cell, 0.375 V for 7T SRAM cell, 0.65 V for 8T SRAM cell, 0.65 V for 9T SRAM cell and 0.6 V for 10T SRAM cell. All the circuit of SRAM cells and their layout has been designed using Cadence virtuoso ADE tool and Cadence virtuoso layout suite respectively using 180 nm CMOS technology. The post layout simulation results have been shown a good agreement with pre layout simulation results.
AB - Data stability and power consumption have been reported two important issues with scaling of CMOS technology. In this paper, we have revisited these issues on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM). The read/write delay and power consumption has been found 0.671/0.267 ns, 1.69 μW for 6T SRAM cell, 0.456/0.752 ns, 1.09 μW for 7T SRAM cell, 0.517/0.392 ns, 1.82 μW for 8T SRAM cell, 0.388/0.181 ns, 1.3 μW for 9T SRAM cell and 0.167/0.242 ns, 2.01 μW for 10T SRAM cell respectively. SNM has been calculated 0.4 V for 6T SRAM cell, 0.375 V for 7T SRAM cell, 0.65 V for 8T SRAM cell, 0.65 V for 9T SRAM cell and 0.6 V for 10T SRAM cell. All the circuit of SRAM cells and their layout has been designed using Cadence virtuoso ADE tool and Cadence virtuoso layout suite respectively using 180 nm CMOS technology. The post layout simulation results have been shown a good agreement with pre layout simulation results.
UR - https://www.scopus.com/pages/publications/84976498245
UR - https://www.scopus.com/pages/publications/84976498245#tab=citedBy
U2 - 10.1007/978-981-10-1023-1_3
DO - 10.1007/978-981-10-1023-1_3
M3 - Conference contribution
AN - SCOPUS:84976498245
SN - 9789811010217
VL - 452
T3 - Advances in Intelligent Systems and Computing
SP - 25
EP - 40
BT - Advanced Computing and Communication Technologies - Proceedings of the 9th ICACCT, 2015
A2 - Nagarajaram, H.A.
A2 - Choudhary, Ramesh K.
A2 - Mandal, Jyotsna Kumar
A2 - Auluck, Nitin
PB - Springer Verlag
T2 - 9th International Conference on Advanced Computing and Communication Technologies, ICACCT 2015
Y2 - 28 November 2015 through 29 November 2015
ER -