Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies

Anand Ilakal; Anuj Grover

doi:10.1007/978-981-10-7470-7_41

Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies

Anand Ilakal^*, Anuj Grover

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The impact of high energy particles in digital memory elements becomes important as technology scales down. The memory elements hold high density latches to store data and these latches are susceptible to disturbs due to particle strikes. The alpha particles, neutrons from cosmic rays may cause Single Event Upset (SEU) in memory cells. In this paper, we propose a method to estimate and compare SER robustness of different layout topologies of SRAM cell. We demonstrate that the radiation hardened layout topologies offer much better Soft Error Rate (SER) robustness compared to conventional layout of the 6-T SRAM cell in 28FDSOI and 40nm technology. The analysis is done using ELDO simulator for a wide range of Linear Energy Transfer (LET) profiles of particle strikes.

Original language	English
Title of host publication	VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers
Editors	Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh
Publisher	Springer Verlag
Pages	414-420
Number of pages	7
ISBN (Print)	9789811074691
DOIs	https://doi.org/10.1007/978-981-10-7470-7_41
Publication status	Published - 01-01-2017
Externally published	Yes
Event	21st International Symposium on VLSI Design and Test, VDAT 2017 - Roorkee, India Duration: 29-06-2017 → 02-07-2017

Publication series

Name	Communications in Computer and Information Science
Volume	711
ISSN (Print)	1865-0929

Conference

Conference	21st International Symposium on VLSI Design and Test, VDAT 2017
Country/Territory	India
City	Roorkee
Period	29-06-17 → 02-07-17

All Science Journal Classification (ASJC) codes

General Computer Science
General Mathematics

Access to Document

10.1007/978-981-10-7470-7_41

Cite this

Ilakal, A., & Grover, A. (2017). Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies. In B. K. Kaushik, S. Dasgupta, & V. Singh (Eds.), VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers (pp. 414-420). (Communications in Computer and Information Science; Vol. 711). Springer Verlag. https://doi.org/10.1007/978-981-10-7470-7_41

Ilakal, Anand ; Grover, Anuj. / Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies. VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers. editor / Brajesh Kumar Kaushik ; Sudeb Dasgupta ; Virendra Singh. Springer Verlag, 2017. pp. 414-420 (Communications in Computer and Information Science).

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title = "Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies",

abstract = "The impact of high energy particles in digital memory elements becomes important as technology scales down. The memory elements hold high density latches to store data and these latches are susceptible to disturbs due to particle strikes. The alpha particles, neutrons from cosmic rays may cause Single Event Upset (SEU) in memory cells. In this paper, we propose a method to estimate and compare SER robustness of different layout topologies of SRAM cell. We demonstrate that the radiation hardened layout topologies offer much better Soft Error Rate (SER) robustness compared to conventional layout of the 6-T SRAM cell in 28FDSOI and 40nm technology. The analysis is done using ELDO simulator for a wide range of Linear Energy Transfer (LET) profiles of particle strikes.",

author = "Anand Ilakal and Anuj Grover",

note = "Publisher Copyright: {\textcopyright} Springer Nature Singapore Pte Ltd 2017.; 21st International Symposium on VLSI Design and Test, VDAT 2017 ; Conference date: 29-06-2017 Through 02-07-2017",

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Ilakal, A & Grover, A 2017, Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies. in BK Kaushik, S Dasgupta & V Singh (eds), VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers. Communications in Computer and Information Science, vol. 711, Springer Verlag, pp. 414-420, 21st International Symposium on VLSI Design and Test, VDAT 2017, Roorkee, India, 29-06-17. https://doi.org/10.1007/978-981-10-7470-7_41

Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies. / Ilakal, Anand; Grover, Anuj.
VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers. ed. / Brajesh Kumar Kaushik; Sudeb Dasgupta; Virendra Singh. Springer Verlag, 2017. p. 414-420 (Communications in Computer and Information Science; Vol. 711).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Grover, Anuj

N1 - Publisher Copyright: © Springer Nature Singapore Pte Ltd 2017.

PY - 2017/1/1

Y1 - 2017/1/1

N2 - The impact of high energy particles in digital memory elements becomes important as technology scales down. The memory elements hold high density latches to store data and these latches are susceptible to disturbs due to particle strikes. The alpha particles, neutrons from cosmic rays may cause Single Event Upset (SEU) in memory cells. In this paper, we propose a method to estimate and compare SER robustness of different layout topologies of SRAM cell. We demonstrate that the radiation hardened layout topologies offer much better Soft Error Rate (SER) robustness compared to conventional layout of the 6-T SRAM cell in 28FDSOI and 40nm technology. The analysis is done using ELDO simulator for a wide range of Linear Energy Transfer (LET) profiles of particle strikes.

AB - The impact of high energy particles in digital memory elements becomes important as technology scales down. The memory elements hold high density latches to store data and these latches are susceptible to disturbs due to particle strikes. The alpha particles, neutrons from cosmic rays may cause Single Event Upset (SEU) in memory cells. In this paper, we propose a method to estimate and compare SER robustness of different layout topologies of SRAM cell. We demonstrate that the radiation hardened layout topologies offer much better Soft Error Rate (SER) robustness compared to conventional layout of the 6-T SRAM cell in 28FDSOI and 40nm technology. The analysis is done using ELDO simulator for a wide range of Linear Energy Transfer (LET) profiles of particle strikes.

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Ilakal A, Grover A. Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies. In Kaushik BK, Dasgupta S, Singh V, editors, VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers. Springer Verlag. 2017. p. 414-420. (Communications in Computer and Information Science). doi: 10.1007/978-981-10-7470-7_41

Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies

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