TY - GEN
T1 - Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies
AU - Ilakal, Anand
AU - Grover, Anuj
N1 - Publisher Copyright:
© Springer Nature Singapore Pte Ltd 2017.
PY - 2017/1/1
Y1 - 2017/1/1
N2 - The impact of high energy particles in digital memory elements becomes important as technology scales down. The memory elements hold high density latches to store data and these latches are susceptible to disturbs due to particle strikes. The alpha particles, neutrons from cosmic rays may cause Single Event Upset (SEU) in memory cells. In this paper, we propose a method to estimate and compare SER robustness of different layout topologies of SRAM cell. We demonstrate that the radiation hardened layout topologies offer much better Soft Error Rate (SER) robustness compared to conventional layout of the 6-T SRAM cell in 28FDSOI and 40nm technology. The analysis is done using ELDO simulator for a wide range of Linear Energy Transfer (LET) profiles of particle strikes.
AB - The impact of high energy particles in digital memory elements becomes important as technology scales down. The memory elements hold high density latches to store data and these latches are susceptible to disturbs due to particle strikes. The alpha particles, neutrons from cosmic rays may cause Single Event Upset (SEU) in memory cells. In this paper, we propose a method to estimate and compare SER robustness of different layout topologies of SRAM cell. We demonstrate that the radiation hardened layout topologies offer much better Soft Error Rate (SER) robustness compared to conventional layout of the 6-T SRAM cell in 28FDSOI and 40nm technology. The analysis is done using ELDO simulator for a wide range of Linear Energy Transfer (LET) profiles of particle strikes.
UR - http://www.scopus.com/inward/record.url?scp=85039448144&partnerID=8YFLogxK
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U2 - 10.1007/978-981-10-7470-7_41
DO - 10.1007/978-981-10-7470-7_41
M3 - Conference contribution
AN - SCOPUS:85039448144
SN - 9789811074691
T3 - Communications in Computer and Information Science
SP - 414
EP - 420
BT - VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers
A2 - Kaushik, Brajesh Kumar
A2 - Dasgupta, Sudeb
A2 - Singh, Virendra
PB - Springer Verlag
T2 - 21st International Symposium on VLSI Design and Test, VDAT 2017
Y2 - 29 June 2017 through 2 July 2017
ER -