Complementary Field Effect Transistor (CFET) for the 2-nm Technology Node: A Review From Device to Circuit Perspectives

The relentless advancement of the semiconductor industry continues to be fueled by the pursuit of enhanced transistor performance. As CMOS technology undergoes aggressive scaling to enable higher integration densities in modern integrated circuits (ICs), there arises a pressing demand for novel device architectures that can minimize cell area without compromising functionality. The complementary-field-effect-transistor (CFET) is emerging as a leading contender to succeed gate-all-around (GAA) FETs beyond the 2-nm technology node, offering a compelling pathway to sustain Moore’s Law into the next era of scaling. Unlike forksheet FET (FSFET) architectures, where nFET and pFET devices are laterally separated, CFETs adopt a vertically stacked configuration. This vertical integration minimizes the required device footprint, constrained primarily by cell height rather than horizontal spacing. As a result, CFETs not only enhance the effective channel width and drive current but also offer the potential for up to a twofold increase in integration density compared to conventional CMOS technologies. This review explores recent advances in CFET architectures, fabrication progress, and associated challenges, exciting prospects in IC design enabled by CFET’s compact structure and vertical integration. Finally, the article highlights critical reliability concerns, emphasizing the need for continued innovation to ensure robust device performance. CFET stands at the forefront of next-generation transistor technologies.