TY - GEN
T1 - Delay and Power Analysis of ALU with 180, 90, and 45 nm Technologies
AU - Karapothula, Rahul Ganesh
AU - Motheesh, J.
AU - Deekshith, T.
AU - Madhushankara, M.
AU - Mathew, Ribu
N1 - Publisher Copyright:
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2026.
PY - 2026
Y1 - 2026
N2 - The optimization of digital circuits is crucial in modern technology; the performance of an electronic device is enhanced by optimizing the power and delay of the circuit. In this paper, an arithmetic and logic unit (ALU) is proposed using transistor-level design in CADENCE using different technologies and analyzed their performance. Using 45 nm technology library, the proposed design achieved a propagation delay of 13.29 ps, an operating frequency of 8.95 GHz, and power dissipation of 0.257 µW.
AB - The optimization of digital circuits is crucial in modern technology; the performance of an electronic device is enhanced by optimizing the power and delay of the circuit. In this paper, an arithmetic and logic unit (ALU) is proposed using transistor-level design in CADENCE using different technologies and analyzed their performance. Using 45 nm technology library, the proposed design achieved a propagation delay of 13.29 ps, an operating frequency of 8.95 GHz, and power dissipation of 0.257 µW.
UR - https://www.scopus.com/pages/publications/105031400249
UR - https://www.scopus.com/pages/publications/105031400249#tab=citedBy
U2 - 10.1007/978-981-95-1058-0_2
DO - 10.1007/978-981-95-1058-0_2
M3 - Conference contribution
AN - SCOPUS:105031400249
SN - 9789819510573
T3 - Lecture Notes in Electrical Engineering
SP - 13
EP - 21
BT - Proceedings of the 4th International Conference on Signal and Data Processing, ICSDP 2024
A2 - Guha, Debatosh
A2 - Adhikari, Debashis
A2 - Suresh, M.
A2 - De, Swades
A2 - Sivasankaran, V.
PB - Springer Science and Business Media Deutschland GmbH
T2 - 4th International Conference on Signal and Data Processing, ICSDP 2024
Y2 - 21 November 2024 through 22 November 2024
ER -