Delay Dynamics of BCD to 7-Segment Converters: A Comparative Study of Single vs. Dual Stage CMOS Architectures

This research work is on study of propagation delay of binary coded decimal (BCD) to 7-segment converter circuit. Two architectures of BCD to 7-segment circuits are designed, one is single stage, and the other is dual stage circuits. Single stage circuit is implemented using static CMOS logic while the dual stage circuit is designed using AND OR logic arrays. BCD to 7-segment converter with four BCD inputs and seven output corresponding to segments a through g are implemented in Cadence Virtuoso simulation tool using gpdk090 with both the architectures. The propagation delay of all seven segments is determined for both the architectures. The output segments a through g for a single stage BCD to 7-segment converter circuit produced a propagation delay of 91.8 ps, 1036.4 ps, 80.69 ps, 95.86 ps, 1158.5 ps, 72.5 ps, and 83.3 ps, respectively. Similarly, the output segments a through g for dual stage BCD to 7-segment converter circuit produced a propagation delay of 92.93 ps, 399.5 ps, 80.68 ps, 102.6 ps, 266.5 ps, 90.83 ps, and 101.1 ps, respectively. Depending on the type of architecture it is found that the output segments a, d, f, and g of single stage converter circuit performed faster with lesser propagation delay as compared to its dual stage version. On the other hand, the output segments b, c, and e of the dual stage have the least propagation delay compared to its corresponding single stage circuit. Our results show the application of respective architectures for high-speed applications in digital VLSI displays and other circuits.