Design & performance analysis of Strained-Si NMOSFET using TCAD

Pramod Martha; Aditya Kumar Hota; Kabiraj Sethi

doi:10.1109/ICETECH.2016.7569390

Design & performance analysis of Strained-Si NMOSFET using TCAD

Pramod Martha
, Aditya Kumar Hota
, Kabiraj Sethi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

Geometric Scaling and high channel doping incorporate loss in mobility. To compensate this, substrate engineering innovations like SOI(Silicon On Insulator) and strained silicon technologies are introduced. In this paper NMOS is designed on Strained Si/relaxed Si_0.8Ge_0.2 heterostructure using TCAD. Electrical analysis of Strained-Si nMOSFET has been done by the ATLAS 2D simulator using low field Arora mobility model. A mobility enhancement factor of 2.6 and transconductance enhancement of 100% at low voltage, compared to that of unstrained -Si control device at room temperature(300K) achieved in this work. Parasitic gate capacitance, the reason for the rise in the delay time has been reduced in the range of 10^-15 F.

Original language	English
Title of host publication	Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	958-961
Number of pages	4
ISBN (Electronic)	9781467399166
DOIs	https://doi.org/10.1109/ICETECH.2016.7569390
Publication status	Published - 15-09-2016
Event	2nd IEEE International Conference on Engineering and Technology, ICETECH 2016 - Coimbatore, India Duration: 17-03-2016 → 18-03-2016

Publication series

Name	Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016

Conference

Conference	2nd IEEE International Conference on Engineering and Technology, ICETECH 2016
Country/Territory	India
City	Coimbatore
Period	17-03-16 → 18-03-16

All Science Journal Classification (ASJC) codes

Computer Networks and Communications

Access to Document

10.1109/ICETECH.2016.7569390

Cite this

Martha, P., Hota, A. K., & Sethi, K. (2016). Design & performance analysis of Strained-Si NMOSFET using TCAD. In Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016 (pp. 958-961). Article 7569390 (Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICETECH.2016.7569390

Martha, Pramod ; Hota, Aditya Kumar ; Sethi, Kabiraj. / Design & performance analysis of Strained-Si NMOSFET using TCAD. Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 958-961 (Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016).

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abstract = "Geometric Scaling and high channel doping incorporate loss in mobility. To compensate this, substrate engineering innovations like SOI(Silicon On Insulator) and strained silicon technologies are introduced. In this paper NMOS is designed on Strained Si/relaxed Si0.8Ge0.2 heterostructure using TCAD. Electrical analysis of Strained-Si nMOSFET has been done by the ATLAS 2D simulator using low field Arora mobility model. A mobility enhancement factor of 2.6 and transconductance enhancement of 100\% at low voltage, compared to that of unstrained -Si control device at room temperature(300K) achieved in this work. Parasitic gate capacitance, the reason for the rise in the delay time has been reduced in the range of 10-15 F.",

author = "Pramod Martha and Hota, \{Aditya Kumar\} and Kabiraj Sethi",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016 ; Conference date: 17-03-2016 Through 18-03-2016",

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Martha, P, Hota, AK & Sethi, K 2016, Design & performance analysis of Strained-Si NMOSFET using TCAD. in Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016., 7569390, Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016, Institute of Electrical and Electronics Engineers Inc., pp. 958-961, 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016, Coimbatore, India, 17-03-16. https://doi.org/10.1109/ICETECH.2016.7569390

Design & performance analysis of Strained-Si NMOSFET using TCAD. / Martha, Pramod; Hota, Aditya Kumar; Sethi, Kabiraj.
Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 958-961 7569390 (Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Martha, Pramod

AU - Hota, Aditya Kumar

AU - Sethi, Kabiraj

PY - 2016/9/15

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N2 - Geometric Scaling and high channel doping incorporate loss in mobility. To compensate this, substrate engineering innovations like SOI(Silicon On Insulator) and strained silicon technologies are introduced. In this paper NMOS is designed on Strained Si/relaxed Si0.8Ge0.2 heterostructure using TCAD. Electrical analysis of Strained-Si nMOSFET has been done by the ATLAS 2D simulator using low field Arora mobility model. A mobility enhancement factor of 2.6 and transconductance enhancement of 100% at low voltage, compared to that of unstrained -Si control device at room temperature(300K) achieved in this work. Parasitic gate capacitance, the reason for the rise in the delay time has been reduced in the range of 10-15 F.

AB - Geometric Scaling and high channel doping incorporate loss in mobility. To compensate this, substrate engineering innovations like SOI(Silicon On Insulator) and strained silicon technologies are introduced. In this paper NMOS is designed on Strained Si/relaxed Si0.8Ge0.2 heterostructure using TCAD. Electrical analysis of Strained-Si nMOSFET has been done by the ATLAS 2D simulator using low field Arora mobility model. A mobility enhancement factor of 2.6 and transconductance enhancement of 100% at low voltage, compared to that of unstrained -Si control device at room temperature(300K) achieved in this work. Parasitic gate capacitance, the reason for the rise in the delay time has been reduced in the range of 10-15 F.

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BT - Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016

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Martha P, Hota AK, Sethi K. Design & performance analysis of Strained-Si NMOSFET using TCAD. In Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 958-961. 7569390. (Proceedings of 2nd IEEE International Conference on Engineering and Technology, ICETECH 2016). doi: 10.1109/ICETECH.2016.7569390

Design & performance analysis of Strained-Si NMOSFET using TCAD

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