TY - GEN
T1 - Design Analysis and Comparative Study of GDI Based Full Adder Design
AU - Yadav, Harsh
AU - Kumar Goyal, Amit
AU - Kumar, Ajay
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/3
Y1 - 2020/3
N2 - In this paper, a 1-bit full adder is implemented using the Gate-Diffusion-Input (GDI) technique and its design analysis is carried out. The design parameters such as delay, power consumption, energy delay product, energy and transistor count are compared with the conventional static CMOS based design. The effect of parasitic capacitance is analyzed via post layout simulation. This reveals that the delay and power consumption of the GDI adder is around 19% and 94% less than to that of CMOS based approach along with reduced number of transistor count.
AB - In this paper, a 1-bit full adder is implemented using the Gate-Diffusion-Input (GDI) technique and its design analysis is carried out. The design parameters such as delay, power consumption, energy delay product, energy and transistor count are compared with the conventional static CMOS based design. The effect of parasitic capacitance is analyzed via post layout simulation. This reveals that the delay and power consumption of the GDI adder is around 19% and 94% less than to that of CMOS based approach along with reduced number of transistor count.
UR - https://www.scopus.com/pages/publications/85091515657
UR - https://www.scopus.com/pages/publications/85091515657#tab=citedBy
U2 - 10.1109/ICSC48311.2020.9182726
DO - 10.1109/ICSC48311.2020.9182726
M3 - Conference contribution
AN - SCOPUS:85091515657
T3 - 2020 6th International Conference on Signal Processing and Communication, ICSC 2020
SP - 319
EP - 321
BT - 2020 6th International Conference on Signal Processing and Communication, ICSC 2020
A2 - Mohan, Jitendr
A2 - Gupta, Abhinav
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Conference on Signal Processing and Communication, ICSC 2020
Y2 - 5 March 2020 through 7 March 2020
ER -