Design and Analysis of a 5-Port Router with Enhanced Features for NoC Applications

With the current generation of System-on-Chip (SoC) designs moving towards having more and more processing cores built into their structures, the demand to have a communication network that can scale up without having to impact timing or predictability has been demanded more and more. Network-on-Chip (NoC) architectures have become a viable option in this sense since they enable parallel transfer of data with reduced interconnect complexity in the whole globe and reduced overall power consumption. The router is at the centre of any NoC, the router controls the movement of flits between nodes and hence contributes significantly to the performance of the network. In this paper, the design and implementation of a five-port QoS-enabled router is proposed in a 2-D mesh NoC. To ensure that traffic with more urgency and that with higher priority than other traffic like real-time data, receives faster access to shared paths when there are conflicts between multiple requests (i.e. not in the same path), the router employs a priority-based arbitration scheme. This assists in addressing latency needs in the busy traffic circumstances. This design is specified in Verilog HDL and its entire design being functionally validated with Cadence Xcelium. In Cadence Genus, synthesis and timing checks are done using typical constraints of SDC. The findings validate proper routing dynamics, one-cycle switching throughput, and significant contention delay reduction in addition to effective utilization of hardware resources. The results of these observations show that the suggested router can be used in performance-sensitive on-chip communication applications in the current SoC platforms.