TY - GEN
T1 - Design and Analysis of Booth Multiplier with Optimised Power Delay Product
AU - Chaitanya, Ch V.S.
AU - Kumar, Psathish
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/8/20
Y1 - 2018/8/20
N2 - In most of the VLSI systems, multiplier being the vital part consumes nearly 15-20% of total IC power and is quiet slow in overall operation of the system. Thus it is essential to have an efficient design for the multipliers to improve the overall performance of the system. Booth multiplier reduces the number of partial products, taking into account two bits of the multiplier at a time, resulting in speed advantage over other multiplier architectures. With this advantage, Booth Multiplier is widely used in multiplication process for various digital and DSP circuits. The objective of this paper is to implement an optimized Booth Multiplier (8∗8) with improved Power consumption and Delay Product (PDP). The sign extension is implemented using a single inverter and the addition operation is implemented by using custom designed Carry Skip Adders with IOT Full Adder. The design implementation and the simulations are done in Cadence Virtuoso V13.0 under 45nm technology.
AB - In most of the VLSI systems, multiplier being the vital part consumes nearly 15-20% of total IC power and is quiet slow in overall operation of the system. Thus it is essential to have an efficient design for the multipliers to improve the overall performance of the system. Booth multiplier reduces the number of partial products, taking into account two bits of the multiplier at a time, resulting in speed advantage over other multiplier architectures. With this advantage, Booth Multiplier is widely used in multiplication process for various digital and DSP circuits. The objective of this paper is to implement an optimized Booth Multiplier (8∗8) with improved Power consumption and Delay Product (PDP). The sign extension is implemented using a single inverter and the addition operation is implemented by using custom designed Carry Skip Adders with IOT Full Adder. The design implementation and the simulations are done in Cadence Virtuoso V13.0 under 45nm technology.
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U2 - 10.1109/ICCCI.2018.8441236
DO - 10.1109/ICCCI.2018.8441236
M3 - Conference contribution
AN - SCOPUS:85053560338
SN - 9781538622384
T3 - 2018 International Conference on Computer Communication and Informatics, ICCCI 2018
BT - 2018 International Conference on Computer Communication and Informatics, ICCCI 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 8th International Conference on Computer Communication and Informatics, ICCCI 2018
Y2 - 4 January 2018 through 6 January 2018
ER -