Design and Analysis of Improved Phase-Transition FinFET Utilizing Negative Capacitance

Sameer Yadav*, Pranshoo Upadhyay, Bhaskar Awadhiya, Pravin N. Kondekar

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

21 Citations (Scopus)

Abstract

Phase transition FinFET (PT-FinFET) is an emerging steep slope device that utilizes phase transition material (PTM) at the source of the host FinFET to achieve steep switching and boost I ON/I OFF ratio compared to conventional transistors. Due to nonzero ρ MET of the assisting PTM, PT-FinFET suffers from low I ON as compared to baseline FinFET. To address this issue, we propose, analyze, and mathematically justify a device design exhibiting enhanced subthreshold swing (SS), I ON and I OFF by exploiting a negative capacitance material at the gate of the PT-FinFET. In the proposed model, critical thickness (fe) of 3 nm for negative capacitance material was achieved. In comparison with the baseline FinFET and negative capacitance PT-FinFET, the proposed device (NC-PT-FinFET) is able to improve I ON I OFF ratio by 3.02 and 2.94 decades, respectively. Furthermore, SS of nearly 10 mV/decade is achieved over 4 decades of drain current with minimum value of 6.8 mV/decade for tfe= 3 nm.

Original languageEnglish
Article number9303433
Pages (from-to)853-859
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume68
Issue number2
DOIs
Publication statusPublished - 02-2021

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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