TY - GEN
T1 - Design and Analysis of LIM Hybrid MTJ/CMOS Logic Gates
AU - Barla, Prashanth
AU - Shet, Deeksha
AU - Joshi, Vinod Kumar
AU - Bhat, Somashekara
PY - 2020/3
Y1 - 2020/3
N2 - Surge in the power dissipation due to increased leakage current has become one of the major concern in conventional CMOS VLSI design because of reduced transistor size, lower threshold voltage and lower supply voltage. To alleviate this, we have designed hybrid magnetic tunnel junction (MTJ)/CMOS circuits based on logic-in-memory (LIM) structure for various logic gates such as NAND/AND, NOR/OR and XNOR/XOR. This paper investigates the performance of hybrid gates and the results are compared with the conventional CMOS based gates in-Terms of power, delay and device count. Hybrid gates designed in this paper are not only non-volatile in nature due to the use of MTJs but also they are found superior than the conventional CMOS circuits by dissipating less power and occupying smaller die area.
AB - Surge in the power dissipation due to increased leakage current has become one of the major concern in conventional CMOS VLSI design because of reduced transistor size, lower threshold voltage and lower supply voltage. To alleviate this, we have designed hybrid magnetic tunnel junction (MTJ)/CMOS circuits based on logic-in-memory (LIM) structure for various logic gates such as NAND/AND, NOR/OR and XNOR/XOR. This paper investigates the performance of hybrid gates and the results are compared with the conventional CMOS based gates in-Terms of power, delay and device count. Hybrid gates designed in this paper are not only non-volatile in nature due to the use of MTJs but also they are found superior than the conventional CMOS circuits by dissipating less power and occupying smaller die area.
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U2 - 10.1109/ICDCS48716.2020.243544
DO - 10.1109/ICDCS48716.2020.243544
M3 - Conference contribution
AN - SCOPUS:85084673171
T3 - ICDCS 2020 - 2020 5th International Conference on Devices, Circuits and Systems
SP - 41
EP - 45
BT - ICDCS 2020 - 2020 5th International Conference on Devices, Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th International Conference on Devices, Circuits and Systems, ICDCS 2020
Y2 - 5 March 2020 through 6 March 2020
ER -