TY - GEN
T1 - Design and Analysis of Low-Power 10 Transistor Full Adders Using Novel XOR XNOR Gates
AU - Akshath, M.
AU - Kumar, Kiran
AU - Shetty, Prashanth Kumar
N1 - Publisher Copyright:
©2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Due to rising power consumption and chip density, low-power VLSI (Very Large-Scale Integration) design is becoming increasingly important for contemporary portable electronic gadgets. The design and analysis of low-power 10-transistor (10T) complete adders using innovative XOR-XNOR gate implementations are presented in this study. By lowering the transistor count compared to a traditional 28-transistor (28T) complete adder model, the suggested design preserves computational accuracy while increasing power efficiency. The 28T and 10T designs are compared in order to assess performance and power usage. According to simulation studies, the 10T model significantly reduces power dissipation, which makes it appropriate for energy-efficient arithmetic circuit applications such as high-performance multipliers and ALUs.
AB - Due to rising power consumption and chip density, low-power VLSI (Very Large-Scale Integration) design is becoming increasingly important for contemporary portable electronic gadgets. The design and analysis of low-power 10-transistor (10T) complete adders using innovative XOR-XNOR gate implementations are presented in this study. By lowering the transistor count compared to a traditional 28-transistor (28T) complete adder model, the suggested design preserves computational accuracy while increasing power efficiency. The 28T and 10T designs are compared in order to assess performance and power usage. According to simulation studies, the 10T model significantly reduces power dissipation, which makes it appropriate for energy-efficient arithmetic circuit applications such as high-performance multipliers and ALUs.
UR - https://www.scopus.com/pages/publications/105034706184
UR - https://www.scopus.com/pages/publications/105034706184#tab=citedBy
U2 - 10.1109/COSMIC67569.2025.11380860
DO - 10.1109/COSMIC67569.2025.11380860
M3 - Conference contribution
AN - SCOPUS:105034706184
T3 - COSMIC 2025 - 2nd IEEE International Conference on Computing, Semiconductor, Mechatronics, Intelligent Systems and Communications, Conference Proceedings
SP - 343
EP - 348
BT - COSMIC 2025 - 2nd IEEE International Conference on Computing, Semiconductor, Mechatronics, Intelligent Systems and Communications, Conference Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd IEEE International Conference on Computing, Semiconductor, Mechatronics, Intelligent Systems and Communications, COSMIC 2025
Y2 - 21 November 2025 through 22 November 2025
ER -