TY - JOUR
T1 - Design and analysis of SHE-assisted STT MTJ/CMOS logic gates
AU - Barla, Prashanth
AU - Joshi, Vinod Kumar
AU - Bhat, Somashekara
N1 - Funding Information:
Prashanth Barla would like to acknowledge the Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal, for providing TMA Pai scholarship for his research work. Part of the work presented in Introduction and Background sections has been already reported and refs. [, , ] and can be used for detailed understanding.
Publisher Copyright:
© 2021, The Author(s).
PY - 2021/10/1
Y1 - 2021/10/1
N2 - We have investigated the spin-Hall effect (SHE)-assisted spin transfer torque (STT) switching mechanism in a three-terminal MTJ device developed using p-MTJ (perpendicular magnetic tunnel junction) and heavy metal materials of high atomic number, which possesses large spin–orbit interaction. Using p-MTJ schematic and complementary-metal-oxide-semiconductor (CMOS) logic, we have designed three basic hybrid logic-in-memory structure-based logic gates NOR/OR, NAND/AND, and XNOR /XOR. Then the performances of these hybrid gates are evaluated and the results are compared with the conventional CMOS-based gates in terms of power, delay, power delay product, and device count. From the analysis, it is concluded that SHE-assisted STT MTJ/CMOS logic gates are nonvolatile, consume less power, and occupy a smaller die area as compared to conventional CMOS only logic gates.
AB - We have investigated the spin-Hall effect (SHE)-assisted spin transfer torque (STT) switching mechanism in a three-terminal MTJ device developed using p-MTJ (perpendicular magnetic tunnel junction) and heavy metal materials of high atomic number, which possesses large spin–orbit interaction. Using p-MTJ schematic and complementary-metal-oxide-semiconductor (CMOS) logic, we have designed three basic hybrid logic-in-memory structure-based logic gates NOR/OR, NAND/AND, and XNOR /XOR. Then the performances of these hybrid gates are evaluated and the results are compared with the conventional CMOS-based gates in terms of power, delay, power delay product, and device count. From the analysis, it is concluded that SHE-assisted STT MTJ/CMOS logic gates are nonvolatile, consume less power, and occupy a smaller die area as compared to conventional CMOS only logic gates.
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U2 - 10.1007/s10825-021-01759-8
DO - 10.1007/s10825-021-01759-8
M3 - Article
AN - SCOPUS:85112823970
SN - 1569-8025
VL - 20
SP - 1964
EP - 1976
JO - Journal of Computational Electronics
JF - Journal of Computational Electronics
IS - 5
ER -