TY - GEN
T1 - Design and Circuit-Level Assessment of Memristor-NMOS for Low-Power Applications
AU - Tejesh, B. S.S.
AU - Tripathy, Manas Ranjan
AU - Ramakrishnan, M.
AU - Darshini, K. Mariya Priya
AU - Sreenivasulu, Vakkalakula Bharat
AU - Singh, Ashish kumar
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This manuscript presents an essential overview of the implementation of memristor-based logic circuits. Different memristor models such as Linear Drift, Simmons Tunnel, Yakopcic, Non-Linear ion Drift, TEAM, and VTEAM have been taken into consideration and a comparison of results has been done adopting all these models. The logic gates such as NAND, NOT, NOR, AND, OR along with some combinational circuits such as a 1-bit comparator, and 2x1 multiplexer were designed and implemented using MRL (Memristor Ratioed Logic) in the LTSpice simulation tool. The primary target of this paper is affirming the attributes of memristor at the device level. Here the logic circuits are implemented using Memristor and NMOS devices. All the circuits designed in this paper operate at a supply voltage of 1V using HP memristor model. Moreover, the power consumed by the designed circuits has been analyzed and found to be in the order of pW.
AB - This manuscript presents an essential overview of the implementation of memristor-based logic circuits. Different memristor models such as Linear Drift, Simmons Tunnel, Yakopcic, Non-Linear ion Drift, TEAM, and VTEAM have been taken into consideration and a comparison of results has been done adopting all these models. The logic gates such as NAND, NOT, NOR, AND, OR along with some combinational circuits such as a 1-bit comparator, and 2x1 multiplexer were designed and implemented using MRL (Memristor Ratioed Logic) in the LTSpice simulation tool. The primary target of this paper is affirming the attributes of memristor at the device level. Here the logic circuits are implemented using Memristor and NMOS devices. All the circuits designed in this paper operate at a supply voltage of 1V using HP memristor model. Moreover, the power consumed by the designed circuits has been analyzed and found to be in the order of pW.
UR - https://www.scopus.com/pages/publications/85218205436
UR - https://www.scopus.com/pages/publications/85218205436#tab=citedBy
U2 - 10.1109/ICIICS63763.2024.10860219
DO - 10.1109/ICIICS63763.2024.10860219
M3 - Conference contribution
AN - SCOPUS:85218205436
T3 - 2nd IEEE International Conference on Integrated Intelligence and Communication Systems, ICIICS 2024
BT - 2nd IEEE International Conference on Integrated Intelligence and Communication Systems, ICIICS 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2nd IEEE International Conference on Integrated Intelligence and Communication Systems, ICIICS 2024
Y2 - 22 November 2024 through 23 November 2024
ER -