Design and Comparative Analysis of FD-SOI FinFET with Dual-dielectric Spacers for High Speed Switching Applications

Moore's law claims that recent technological developments have already resulted in a significant rise in the number of transistors on a chip. By switching from a conventional MOSFET built with a single control gate to one with numerous control gates, the device's manageability has been significantly improved. Apart from this dielectric spacer plays a vital role in enhancing the device's performance drastically. This work compares the performance of fully depleted Silicon on Insulator (SOI) FinFETs constructed with single-k and dual-k dielectric spacers, adjusting the channel doping concentration as 1 × 10¹⁹/cm³, 1 × 10¹⁸ /cm³, and 1 × 10¹⁷ /cm³. Among the single dielectric spacers investigated are air, SiO₂, HfO₂, and a dual spacer combination with HfO₂+SiO₂ between the source (S) and drain (D) terminals. The leakage current will be successfully reduced, and short channel effects (SCEs) will be improved with FinFETs that include dual dielectric spacer dielectric materials in the design. The performance of CMOS inverter for various dielectrics is also performed and its effect on a single dielectric spacer is analyzed. The performance of the designed FinFET with single-k and dual-k spacers is analyzed using the Visual-TCAD 3D Cogenda tool and circuit aspects are performed using the CADENCE platform. Exciting device DC properties are established, including I_ON to I_OFF ratio of 10⁵, DIBL of 13 mV/V, sub-threshold swing (SS) of 72 mV/dec, and low threshold voltage (V_th) of 0.16 V for channel doping concentration of 1 × 10¹⁹ cm⁻³ of the dual-k HfO₂+SiO₂ spacer combination. Single spacer dielectrics are effective for low power, while multiple spacer dielectrics efficiently limit leakages and effectively increase switching speed.