Design and deep insights into sub-10 nm spacer engineered junctionless FinFET for nanoscale applications

In this paper, we have studied the impact of various dielectric single-k (S-k) and dual-k (D-k) spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric oxide based (HfxTi1-xO2) gate stack to enhance the sub-threshold performance of the device. Performance impact of outer low-k spacer variation on D-k spacer by fixing inner high-k spacer has been reported. In this move, it is noticed that the ION/IOFF ratio shifted from 8.70 × 105 to 1.30 × 106 which is about ∼1.5x times improvement. Along with DC characteristics, analog/RF and linearity metrics are extracted and analysed. Due to a better gate electrostatic integrity (EI) at an extremely scaled LG, an optimally designed D-k spacer reveals a better DC and analog performance characteristics. The S-k spacer reveals a better performer in power consumption, dynamic power, RF, and linearity characteristics at nano scale. Furthermore, the scaling possibilities by spacers on DC and Analog performance at LG = 10 nm FinFET with tri-gate geometry at LG of 7 nm, 5 nm, and 3 nm are also examined. It has been noticed that the enhanced performance with the tri-gate structure is best suitable for future technological nodes.