TY - JOUR
T1 - Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure
AU - Barla, Prashanth
AU - Joshi, Vinod Kumar
AU - Bhat, Somashekara
N1 - Publisher Copyright:
© 2022 World Scientific Publishing Company.
PY - 2022/5/30
Y1 - 2022/5/30
N2 - In this paper, a power-efficient self write-terminated hybrid full-adder (SWTHFA) has been developed using the self write-terminated write driver and an improved version of the sense amplifier already reported in the literature. The SWTHFA is designed using hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuit based on logic-in-memory architecture. The use of a modified sense amplifier improves the power dissipation and output response on one hand, whereas, on the other hand, self-write-terminated write driver cuts off the unnecessary flow of write current in the driver circuit, thereby eliminates power wastage in SWTHFA. Proposed SWTHFA shows improvement in power saving, output response, read and write power delay product by 38.87%, 26.45%, 40.86% and 36.53%, respectively, compared to conventional write hybrid full-adder (CWHFA). Further, we performed Monte-Carlo simulations by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ to demonstrate the feasibility of SWTHFA in low-power VLSI circuits.
AB - In this paper, a power-efficient self write-terminated hybrid full-adder (SWTHFA) has been developed using the self write-terminated write driver and an improved version of the sense amplifier already reported in the literature. The SWTHFA is designed using hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuit based on logic-in-memory architecture. The use of a modified sense amplifier improves the power dissipation and output response on one hand, whereas, on the other hand, self-write-terminated write driver cuts off the unnecessary flow of write current in the driver circuit, thereby eliminates power wastage in SWTHFA. Proposed SWTHFA shows improvement in power saving, output response, read and write power delay product by 38.87%, 26.45%, 40.86% and 36.53%, respectively, compared to conventional write hybrid full-adder (CWHFA). Further, we performed Monte-Carlo simulations by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ to demonstrate the feasibility of SWTHFA in low-power VLSI circuits.
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U2 - 10.1142/S0218126622501468
DO - 10.1142/S0218126622501468
M3 - Article
AN - SCOPUS:85124714361
SN - 0218-1266
VL - 31
JO - Journal of Circuits, Systems and Computers
JF - Journal of Circuits, Systems and Computers
IS - 8
M1 - 2250146
ER -