Design and Implementation of 16-Bit Optimized RISC Processor with Novel Pipelining

In the modern era, improvement in the quality of the processor plays a vital role in SoC designing. Understanding and designing of RISC (Reduced Instruction Set Computer) processor, ARM-based processor plays a vital role in the semiconductor domain since it’s being used in various devices across like smartphones, supercomputers, etc. In this paper, an optimized 16-bit RISC processor is proposed with the concept of pipelining and clock gating, which utilizes minimum on-chip power with maximum throughput achieved. The proposed design is based on the architecture that has separate blocks like Program Counter, Multiplexer, Instruction Memory, Data Memory, Arithmetic Logic Unit (ALU), Decoders, Registers, Flag Register, Adders, and various pipelines added. This processor supports 16 instructions with each instruction as 24-bit wide. In the register file, it has a total of 16 registers with each register as 16-bit. 16-bit ALU has been used in the design, which supports a total of 11 operations. It also incorporates a three-bit register, which can detect carry, zero, and parity status of the result given by ALU. This processor executes instruction in four stages: idle, fetch, decode, and execute. All the modules/sub-modules in the design are coded in Verilog HDL. Proper mapping is done between various modules to form the top/final module of RISC processor after proper checking of the functionality of sub-modules. Functional verification and synthesis are done using Xilinx Vivado tool, and the simulation results have been collected from the same.