TY - GEN
T1 - Design and Implementation of 32-bit Functional Unit for RISC architecture applications
AU - Samanth, Rashmi
AU - Amin, Ashwini
AU - Nayak, Subramanya G.
PY - 2020/3
Y1 - 2020/3
N2 - This paper presents the design and implementation of 32-bit Functional unit which is used for RISC based processor. This includes designing of processor modules such as Arithmetic and Logic unit (ALU) which realizes addition, subtraction, multiplication, shifting and code conversion by suitable control units and data paths. Multiplexers are used for selecting various operations based on the control inputs. These functional blocks are developed using the Hardware Description Language (HDL). Simulation and synthesis of each block is carried using Xilinx ISE to analyze the results. Results of proposed design has been compared with the conventional Microprocessor without interlocked Pipeline Stages (MIPS) which shows reduction in power dissipation by 30.449%, area by 6% and delay by 34.49%.
AB - This paper presents the design and implementation of 32-bit Functional unit which is used for RISC based processor. This includes designing of processor modules such as Arithmetic and Logic unit (ALU) which realizes addition, subtraction, multiplication, shifting and code conversion by suitable control units and data paths. Multiplexers are used for selecting various operations based on the control inputs. These functional blocks are developed using the Hardware Description Language (HDL). Simulation and synthesis of each block is carried using Xilinx ISE to analyze the results. Results of proposed design has been compared with the conventional Microprocessor without interlocked Pipeline Stages (MIPS) which shows reduction in power dissipation by 30.449%, area by 6% and delay by 34.49%.
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U2 - 10.1109/ICDCS48716.2020.243545
DO - 10.1109/ICDCS48716.2020.243545
M3 - Conference contribution
AN - SCOPUS:85084642616
T3 - ICDCS 2020 - 2020 5th International Conference on Devices, Circuits and Systems
SP - 46
EP - 48
BT - ICDCS 2020 - 2020 5th International Conference on Devices, Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th International Conference on Devices, Circuits and Systems, ICDCS 2020
Y2 - 5 March 2020 through 6 March 2020
ER -