Design and Implementation of Cordic based Digital Modulation Techniques using DPLL

H. D. Nataraj Urs; B. N. Aravind; K. Krishna Veni; N. Yashwanth

doi:10.1109/TEMSMET56707.2023.10150192

Design and Implementation of Cordic based Digital Modulation Techniques using DPLL

H. D. Nataraj Urs^*, B. N. Aravind, K. Krishna Veni, N. Yashwanth

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This document delineates the implementation of Cordic based FPGA digital modulation techniques using DPLL for great-resolution digital communication applications. We are emphasizing upon digital phase lock loop-based Verilog-based code simulation for routinely adopted digital modulation techniques. In this work, based on the fundamental principles of sampling and quantization of DPLL digital signals, the sine wave which have been produced is smooth and plain in nature. Modelsim and Xilinx-ISE are used to run the simulation, which uses the VERILOG Hardware description language. A 32-bit serial data transmission system with self-adjusting carrier frequency and bit length has been developed.

Original language	English
Title of host publication	3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350397819
DOIs	https://doi.org/10.1109/TEMSMET56707.2023.10150192
Publication status	Published - 2023
Event	3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023 - Mysuru, India Duration: 10-02-2023 → 11-02-2023

Publication series

Name	3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023

Conference

Conference	3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023
Country/Territory	India
City	Mysuru
Period	10-02-23 → 11-02-23

All Science Journal Classification (ASJC) codes

Marketing
Organizational Behavior and Human Resource Management
Strategy and Management
Artificial Intelligence
Computer Science Applications
Information Systems and Management
Control and Optimization
Health Informatics

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/TEMSMET56707.2023.10150192

Cite this

Nataraj Urs, H. D., Aravind, B. N., Krishna Veni, K., & Yashwanth, N. (2023). Design and Implementation of Cordic based Digital Modulation Techniques using DPLL. In 3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023 (3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEMSMET56707.2023.10150192

Nataraj Urs, H. D. ; Aravind, B. N. ; Krishna Veni, K. et al. / Design and Implementation of Cordic based Digital Modulation Techniques using DPLL. 3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023).

@inproceedings{37542000662c4833bd35e2ab579a6ffd,

title = "Design and Implementation of Cordic based Digital Modulation Techniques using DPLL",

abstract = "This document delineates the implementation of Cordic based FPGA digital modulation techniques using DPLL for great-resolution digital communication applications. We are emphasizing upon digital phase lock loop-based Verilog-based code simulation for routinely adopted digital modulation techniques. In this work, based on the fundamental principles of sampling and quantization of DPLL digital signals, the sine wave which have been produced is smooth and plain in nature. Modelsim and Xilinx-ISE are used to run the simulation, which uses the VERILOG Hardware description language. A 32-bit serial data transmission system with self-adjusting carrier frequency and bit length has been developed.",

author = "\{Nataraj Urs\}, \{H. D.\} and Aravind, \{B. N.\} and \{Krishna Veni\}, K. and N. Yashwanth",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023 ; Conference date: 10-02-2023 Through 11-02-2023",

year = "2023",

doi = "10.1109/TEMSMET56707.2023.10150192",

language = "English",

series = "3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023",

address = "United States",

}

Nataraj Urs, HD, Aravind, BN, Krishna Veni, K & Yashwanth, N 2023, Design and Implementation of Cordic based Digital Modulation Techniques using DPLL. in 3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023. 3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023, Institute of Electrical and Electronics Engineers Inc., 3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023, Mysuru, India, 10-02-23. https://doi.org/10.1109/TEMSMET56707.2023.10150192

Design and Implementation of Cordic based Digital Modulation Techniques using DPLL. / Nataraj Urs, H. D.; Aravind, B. N.; Krishna Veni, K. et al.
3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Design and Implementation of Cordic based Digital Modulation Techniques using DPLL

AU - Nataraj Urs, H. D.

AU - Aravind, B. N.

AU - Krishna Veni, K.

AU - Yashwanth, N.

PY - 2023

Y1 - 2023

N2 - This document delineates the implementation of Cordic based FPGA digital modulation techniques using DPLL for great-resolution digital communication applications. We are emphasizing upon digital phase lock loop-based Verilog-based code simulation for routinely adopted digital modulation techniques. In this work, based on the fundamental principles of sampling and quantization of DPLL digital signals, the sine wave which have been produced is smooth and plain in nature. Modelsim and Xilinx-ISE are used to run the simulation, which uses the VERILOG Hardware description language. A 32-bit serial data transmission system with self-adjusting carrier frequency and bit length has been developed.

AB - This document delineates the implementation of Cordic based FPGA digital modulation techniques using DPLL for great-resolution digital communication applications. We are emphasizing upon digital phase lock loop-based Verilog-based code simulation for routinely adopted digital modulation techniques. In this work, based on the fundamental principles of sampling and quantization of DPLL digital signals, the sine wave which have been produced is smooth and plain in nature. Modelsim and Xilinx-ISE are used to run the simulation, which uses the VERILOG Hardware description language. A 32-bit serial data transmission system with self-adjusting carrier frequency and bit length has been developed.

UR - https://www.scopus.com/pages/publications/85164271530

UR - https://www.scopus.com/inward/citedby.url?scp=85164271530&partnerID=8YFLogxK

U2 - 10.1109/TEMSMET56707.2023.10150192

DO - 10.1109/TEMSMET56707.2023.10150192

M3 - Conference contribution

AN - SCOPUS:85164271530

T3 - 3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023

BT - 3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023

Y2 - 10 February 2023 through 11 February 2023

ER -

Nataraj Urs HD, Aravind BN, Krishna Veni K, Yashwanth N. Design and Implementation of Cordic based Digital Modulation Techniques using DPLL. In 3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (3rd IEEE International Conference on Technology, Engineering, Management for Societal Impact using Marketing, Entrepreneurship and Talent, TEMSMET 2023). doi: 10.1109/TEMSMET56707.2023.10150192

Design and Implementation of Cordic based Digital Modulation Techniques using DPLL

Abstract

Publication series

Conference

All Science Journal Classification (ASJC) codes

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this