TY - JOUR
T1 - Design and Implementation of Power-Efficient FSM based UART
AU - Kamath, Akshatha
AU - Mendez, Tanya
AU - Ramya, S.
AU - Nayak, Subramanya G.
N1 - Funding Information:
The first author would like to thank and acknowledge the Manipal Institute of Technology, Manipal Academy of Higher Education (MAHE), Manipal, for successfully implementing this work. The authors are also thankful to the Department of Electronics and Communication Engineering for providing the facilities for smooth conduction of the laboratory work.
Publisher Copyright:
© 2022 Institute of Physics Publishing. All rights reserved.
PY - 2022/1/11
Y1 - 2022/1/11
N2 - The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.
AB - The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.
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U2 - 10.1088/1742-6596/2161/1/012052
DO - 10.1088/1742-6596/2161/1/012052
M3 - Conference article
AN - SCOPUS:85124704919
SN - 1742-6588
VL - 2161
JO - Journal of Physics: Conference Series
JF - Journal of Physics: Conference Series
IS - 1
M1 - 012052
T2 - 1st International Conference on Artificial Intelligence, Computational Electronics and Communication System, AICECS 2021
Y2 - 28 October 2021 through 30 October 2021
ER -