Design of a 4-Bit carry select adder with high speed and low power using 45 nm technology

Modern VLSI design relies heavily on high-speed, low-power digital systems, which makes arithmetic unit optimization crucial. Of these, adders have a major impact on how well microprocessors and digital signal processors perform. One well-known method for reducing carry propagation delay, a major performance bottleneck, is the carry select adder (CSA). However, speed, power, and area are frequently traded off in traditional CSA designs. An optimized 4-bit CSA for high-speed and low-power applications is presented in this project. A hybrid logic approach is used in the suggested design. For dependable and effective operation, propagate and generate signals are calculated using C²MOS logic. While XOR and XNOR gates use transmission gate logic to cut down on power and delay, basic gates like AND, NAND, OR, and NOR are implemented using static complementary metal–oxide–semiconductor (CMOS) logic. The correct sum output is chosen by a final dynamic logic-based 2:1 multiplexer that is managed by the carry-in signal. 45 nm CMOS technology is used to implement the design. In terms of power-delay products and area efficiency, the optimized CSA performs better than traditional adders, confirming its appropriateness for high-performance and energy-constrained applications.